This invention is in the field of semiconductor integrated circuit manufacturing, and is more specifically directed to the photolithographic patterning and etch of device features.
In the field of integrated circuit manufacturing, a fundamental goal to design and manufacture integrated circuits to be as small as possible. As is well known in this art, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit die or chip. This is because the chip area correlates directly to the number of possible integrated circuits per manufactured wafer, and because the theoretical yield, for a given manufacturing defect density, increases as chip area decreases. In addition, smaller feature sizes result in improved device performance and increased functionality for a given chip area.
In the manufacture of metal-oxide-semiconductor (MOS) integrated circuits, the gate electrode is typically the physical feature that is the smallest feature defined by a photolithographic pattern. As fundamental in the art, the size of the gate electrode in turn defines the MOS transistor channel length, which is an important physical parameter in defining both the device density and also the transistor performance in an MOS integrated circuit. Indeed, specific processing technologies are typically referred to by the nominal transistor channel length. And in turn, the transistor gate electrode width is often referred to as a “critical dimension” or “CD” feature of the integrated circuit.
Conventional photolithography processes are used to form integrated circuit features. As is fundamental in the art, photolithography involves the exposure to light of a photosensitive material, typically a photosensitive polymer film referred to as photoresist, that is dispensed over the material that is to be selectively etched in forming the integrated circuit at the surface of a semiconductor substrate (typically a semiconductor wafer). After exposure of the photoresist to light, through a photomask or reticle, and subsequent developing, selected portions of the photoresist film are removed to leave cross-linked photoresist structures in a pattern corresponding to the pattern of the photomask. The remaining photoresist pattern defines the locations of the underlying material that are to be protected from a subsequent etch, in turn defining the locations of the integrated circuit structures to be formed from that material. In some cases, the photoresist masks the etch of an insulating material that itself becomes a mask (i.e., a “hard” mask) of the etch of another layer underlying that insulating material. Either through the action of the etch itself, or a subsequent cleanup or ash, any remaining photoresist is removed from the wafer prior to the next deposition or other manufacturing process.
In recent years, the “critical dimension” of MOS transistor gate widths has become significantly smaller than 500 nm. These small dimensions have been attained using photolithography, despite the recurring predictions that photolithography is limited in the feature sizes that it can define. These predictions have proven false because of important advances in the field, including the use of ever-shorter wavelengths of light, the use of more complex photomasks (e.g., phase-shift photomasks), anti-reflective coatings, and the like.
In addition, certain etch techniques are used to form features that are even smaller than those that can be photolithographically defined, such features sometimes referred to as “sub-lithographic” features. These conventional processes typically involve post-development blanket reduction of the size of the masking features. FIGS. 1a through 1d illustrate, in cross-section, an example of such a conventional process, for the typical example of forming a sub-lithographic polysilicon gate electrode.
FIG. 1a illustrates substrate 2, and overlying gate dielectric layer 3. Polysilicon layer 4 overlies gate dielectric layer 3, and is the layer that will be patterned and etched according to this conventional photolithographic process. In this example, a two-layer hardmask will be in place during the polysilicon etch. Silicon-rich silicon nitride layer 6 overlies polysilicon layer 4, and silicon-oxynitride layer 8 overlies silicon-rich nitride layer 6. The relative thicknesses of silicon-rich nitride layer 6 and silicon-oxynitride layer 8 are selected, in this conventional example, to minimize reflections of the light in the photolithographic exposure. As is also shown in FIG. 1a, photoresist 10 overlies a portion of silicon oxynitride layer 8, at a location corresponding to the location of the eventual gate electrode to be formed in polysilicon layer 4. At the stage shown in FIG. 1a, photoresist 10 has been exposed to masked electromagnetic energy (typically of a wavelength in the so-called “deep UV” range), and has been developed so that photoresist 10 in its cross-linked state remains in the desired pattern, with the remainder of the photoresist (not cross-linked by the exposure and development) removed from the structure. Photoresist 10 may either be of the positive or negative type, with the corresponding photomask or reticle (i.e., positive or negative) used during exposure.
Typically, the width W of the remaining photoresist element 10 is at or near the smallest dimension that can be photolithographically patterned. According to current technology, this width W is about 100 nm. However, in this example, the eventual width of the gate electrode to be formed in polysilicon layer 4 is substantially narrower than this 100 nm photolithographic limit. According to this conventional method, therefore, photoresist element 10 is “trimmed”, or narrowed, by way of a timed isotropic etch. The result of this trim operation is illustrated in FIG. 1b, with trimmed photoresist element 10′ shown. As evident from FIG. 1b, the isotropic nature of this trim etches into both sides of photoresist 10, and also reduces its thickness from the top by an amount approximately one-half of its width reduction. The new width W′ of trimmed photoresist element 10′ may be on the order of 50 nm.
After the trim operation illustrated in FIG. 1b, photoresist element 10′ is then used to mask the etch of the underlying hardmask layers including, in this example, silicon oxynitride layer 8 and silicon-rich nitride layer 6. This etch is preferably an anisotropic etch, so that the dimension of the resulting hardmask corresponds to that of trimmed photoresist element 10′. The result of this etch is illustrated in FIG. 1c, with the remaining portions of silicon oxynitride layer 8 and silicon-rich nitride layer 6 remaining in place over polysilicon layer 4 at the location defined by photoresist 10. As evident from FIG. 1c, the completion of this etch can thin silicon oxynitride layer 8.
Polysilicon layer 4 is then anisotropically etched, using the remaining hardmask of silicon oxynitride layer 8 and silicon-rich nitride layer 6 to protect the eventual location of the polysilicon gate electrode. The protected portion of polysilicon 4 as a transistor gate electrode is illustrated in FIG. 1d. Some portion of the hardmask, most likely the lower silicon-rich nitride layer 8 but also possibly including silicon oxynitride layer 8, remains over the gate electrode as shown in FIG. 1d; this residue will be removed by a subsequent cleanup or etch, to permit contact to polysilicon 4 (at a wider location than that shown in FIG. 1d).
This conventional defining of the critical dimension feature of the polysilicon gate electrode, using the trimming of photoresist, works well in theory. In practice, however, especially considering the extremely narrow feature sizes and the relatively large film thicknesses for those small features, this conventional approach has some significant limitations.
A first limitation is illustrated in FIG. 1e, in which post-trim photoresist element 10″ is illustrated. If the aspect ratio of height (thickness) to width of photoresist element 10″ is too high, such as 3:1 or higher, photoresist element 10″ may not be able to structurally survive the trim operation. More specifically, stress deformation of photoresist element 10″ occurs as a result of the trim, causing photoresist element 10″ to lean to one side and, in the extreme case, to detach and fall. As a result, deformed photoresist element 10″ cannot properly protect nor accurately define the hardmask of the underlying silicon oxynitride layer 8 and silicon-rich nitride layer 6. Completion of the polysilicon etch process results in unduly narrowed, broken, or even completely missing polysilicon gate electrode structures, as illustrated in the plan view of FIG. 1f. As shown in FIG. 1f, polysilicon gate electrodes 4″ are broken as they extend over moat region 5 (i.e., the location of source and drain diffusions) between wider polysilicon contact structures 4. Obviously, in the case of FIG. 1f, the broken and narrowed polysilicon gate electrodes 4″ are not capable of operating as transistor gate electrodes to control the current between opposing sides of moat region 5 (i.e., the source and drain).
Even if the structural integrity of photoresist elements 10″ can be maintained, this conventional process has other limitations. As described above, the hard mask layers include both silicon oxynitride layer 8 and silicon-rich nitride layer 6, of thicknesses that are selected to eliminate optical reflections during exposure, which constrains the selection of film thicknesses. But silicon oxynitride layer 8 is difficult to remove with a wet cleanup after polysilicon etch, Accordingly, in the conventional process of FIGS. 1a through 1d, the polysilicon etch must be designed so that silicon oxynitride layer 8 is fully consumed by the time that the etch is completed. This constraint on the etch process has been observed to limit the performance of the etch of polysilicon layer 4 itself, resulting in less-than-optimal defining of the polysilicon gate electrodes and other critical dimension features.